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f OCnxPCPWM = ----------------------------
ATmega128
the counter decrements. The P W M frequency for the output when using phase correct P W M can
be calculated by the following equation:
f clk_I/O
2 ? N ? TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a P W M
waveform output in the phase correct P W M mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted P W M mode. For inverted P W M the output will have the opposite logic values.
If OCnA is used to define the TOP value ( W GMn3:0 = 11) and COMnA1:0 = 1, the OCnA Output
will toggle with a 50% duty cycle.
Phase and Frequency
Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct P W M
mode ( W GMn3:0 = 8 or 9) provides a high resolution phase and frequency correct P W M wave-
R PFCPWM = ----------------------------------
form generation option. The phase and frequency correct P W M mode is, like the phase correct
P W M mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the
output compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while
counting up, and set on the compare match while downcounting. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-
quency compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope P W M modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct P W M
mode is the time the OCRnx Register is updated by the OCRnx buffer Register, (see Figure 53
and Figure 54 ).
The P W M resolution for the phase and frequency correct P W M mode can be defined by either
ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and
the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The P W M resolution in bits can
be calculated using the following equation:
log ( 2 )
In phase and frequency correct P W M mode the counter is incremented until the counter value
matches either the value in ICRn ( W GMn3:0 = 8), or the value in OCRnA ( W GMn3:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNTn value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct P W M mode is shown on Figure 54 . The figure shows phase and frequency correct P W M
mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram
shown as a histogram for illustrating the dual-slope operation. The diagram includes non-
inverted and inverted P W M outputs. The small horizontal line marks on the TCNTn slopes repre-
sent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a
compare match occurs.
128
2467X–AVR–06/11
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